Contact Information
From
February 18th, 2025
To
February 20th, 2025
Wafer-Level Packaging Symposium 2025
Event Information
The Wafer-Level Packaging Symposium brings together the semiconductor industry's leading experts to explore the latest advancements in wafer-level, 3D device packaging, advanced manufacturing, and test technologies. This event will be held in the heart of Silicon Valley, offering attendees from around the globe the opportunity to be at the forefront of packaging technology evolution.
The symposium will feature a variety of activities, including keynote speakers, panel discussions, and workshops. Attendees will have the chance to network with industry professionals and gain valuable insight into the latest trends and developments in the field. Additionally, the symposium provides a unique platform for exhibitors to showcase their products and services to a highly engaged audience.
The Wafer-Level Packaging Symposium is the perfect opportunity for industry professionals to stay informed and stay ahead of the competition. Join us in San Francisco, CA, United States to explore the latest in wafer-level packaging, 3D, and advanced manufacturing & test technologies.
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Organizer(s)
Surface Mount Technology Association (SMTA)
Available Booths
Location
1333 Bayshore Highway, Burlingame, California, San Francisco CA, United States, United States
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Floor Plan(s)
Supporting documents (if any)
Other editions
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The Wafer-Level Packaging Symposium 2025 will be held in the heart of Silicon Valley, San Francisco CA, United States. It will bring together the semiconductor industry's most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test techno...
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